Non-blocking assignment

module top();
reg A1,A2,B1,B2;

initial begin //Non-blocking assignment
A1=1;
B1=0;
A1<=B1;
B1<=A1;
end

initial begin //Blocking assignment
A2=1;
B2=0;
A2=B2;
B2=A2;
end

initial begin
$monitor("A1=%b B1=%b A2=%b B2=%b",A1,B1,A2,B2);
end

endmodule

Time scales Ex.3

`timescale 1ns/1ps
module The_first_module(y,x1,x2);
input x1,x2;
output y;

nand #(3.213:3.225:3.643,4.112:4.237:4.413) (y,x1,x2);
endmodule


`timescale 10ns/10ns
module The_second_module();
reg x1,x2;
wire y;

The_first_module K1(y,x1,x2);

initial begin
$timeformat(-12,1," ps",10);
$monitor($time,,"%f x1=%b x2=%b y=%b",$realtime,x1,x2,y);
end

initial #30 $finish;

initial begin
#5 x1=0;x2=0;
#5 x2=1;
#5 x1=1;
#5 x2=0;
#5 $stop;
end
endmodule

Time scales Ex.2

`timescale 1ns/1ps
module The_first_module(y,x1,x2);
input x1,x2;
output y;

nand #(3.213:3.225:3.643,4.112:4.237:4.413) (y,x1,x2);
endmodule


`timescale 10ns/10ns
module The_second_module();
reg x1,x2;
wire y;

The_first_module K1(y,x1,x2);

initial begin
$timeformat(-10,1,"x100ps",10);
$monitor($time,,"%f x1=%b x2=%b y=%b",$realtime,x1,x2,y);
end

initial #30 $finish;

initial begin
#5 x1=0;x2=0;
#5 x2=1;
#5 x1=1;
#5 x2=0;
#5 $stop;
end
endmodule

Time Scales Ex.1

`timescale 1ns/10ps
module The_first_module(y,x1,x2);
input x1,x2;
output y;

nand #(3.213:3.225:3.643,4.112:4.237:4.413) (y,x1,x2);
endmodule


`timescale 10ns/10ns
module The_second_module();
reg x1,x2;
wire y;

The_first_module K1(y,x1,x2);

initial begin
$timeformat(-10,1," x100ps",10);
$monitor($time,,"%f x1=%b x2=%b y=%b",$realtime,x1,x2,y);
end

initial #30 $finish;

initial begin
#5 x1=0;x2=0;
#5 x2=1;
#5 x1=1;
#5 x2=0;
#5 $stop;
end
endmodule

1位元全加法器(with UDP)

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
system_clock #200 clock1(c_in);

Adder_Sum D1(sum,a,b,c_in);
Adder_C D2(c,a,b,c_in);
endmodule

primitive Adder_Sum(Sum,A,B,C_in);
output Sum;
input C_in,A,B;

table
// C_in A B : Sum
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 0;
1 1 1 : 1;
endtable
endprimitive

primitive Adder_C(C,A,B,C_in);
output C;
input C_in,A,B;
table
// C_in A B : C
0 0 0 : 0;
0 0 1 : 0;
0 1 0 : 0;
0 1 1 : 1;
1 0 0 : 0;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;

endtable
endprimitive

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

危障

module top;
wire f,c_bar,d,e,f0,f1;
reg a,b,c;
initial
begin
#10 a=1; b=1;
#10 c=1;
#10 c=0;
end
initial
#100 $finish;


AND_gate xxx(f0,a,c);
NOT xxx1(c_bar,c);
AND_gate xxx2(f1,b,c_bar);
or_data xx(f,f0,f1);

AND_gate xxx3(f3,a,b);
AND_gate xxx(f4,a,c);
AND_gate xxx2(f5,b,c_bar);
or_data2 xx1(f2,f3,f4,f5);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module NOT(c_bar,c);
input c;
output c_bar;
wire c;
not(c_bar,c);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(c=>c_bar)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data(f,f0,f1);
input f0,f1;
output f;
wire f;
or(f,f0,f1);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f0=>f)=(Tpd_0_1,Tpd_1_0);
(f1=>f)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data2(f2,f3,f4,f5);
input f3,f4,f5;
output f2;
wire f2;

or(f2,f3,f4,f5);

specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f3=>f2)=(Tpd_0_1,Tpd_1_0);
(f4=>f2)=(Tpd_0_1,Tpd_1_0);
(f5=>f2)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

32位元加法 Ver.未測試1

module top;
wire c_out,c_in,c_out2;
reg [31:0]a,b,a2,b2;
wire [31:0]sum,sum2;
integer a1,b1,a11,b11;

system_clock #200 clock9(c_in);

initial
begin
for(a1=0;a1<65536;a1=a1+1)
begin
for(a11=0;a11<65536;a11=a11+1)
begin
for (b1=0;b1<65536;b1=b1+1)
begin
for (b11=0;b11<65536;b11=b11+1)
begin
{b}=b11;
{a}=a11;
{b2}=b11;
{a2}=a11;
#1;
end
end
end
end
$finish;
end
Adder_x #32 K1(sum,c_out,a,b,c_in);
assign {c_out2,sum2}=a2+b2+c_in;
always@(a2 or b2 or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o,a2=%o,a1=%o,b2=%o,b1=%o",sum,sum2,a2,a,b2,b);
else
$display ("c_out=%b,c_out2=%b,a2=%o,a1=%o,b2=%o,b1=%o",c_out,c_out2,a2,a,b2,b);
end
endmodule



module Adder_x(sum,c_out,a,b,c_in);
parameter size=4;
input [size-1:0]a,b,c_in;
output [size-1:0]sum;
output c_out;

assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

期中考

A0 A1 B0 B1 F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

F={A0(~B0)(~B1)}+{A0(~A1)(~B0)}+{(~A0)A1(~B0)B1}+{(~A0)(~A1)B0B1}+{A0A1B0B1}

={A0(~B0)[(~A1)+(~B1)]} + {A1B1[(~A0)(~B0)+A0B0]} + {(~A0)(~A1)B0B1}

====================================================

module top;
wire A0,A1,B0,B1;
wire F;

system_clock #100 X1(B1);
system_clock #200 X1(B0);
system_clock #400 X1(A1);
system_clock #800 X1(A0);

testing1 Z1(F,A0,A1,B0,B1);
endmodule

module testing1(F,A0,A1,B0,B1);
input A0,A1,B0,B1;
output F;
wire [11:1] w;

not (w[1],A0);
not (w[2],A1);
not (w[3],B0);
not (w[4],B1);
and (w[5],A0,w[3]);
or (w[6],w[2],w[4]);
and (w[7],w[5],w[6]);
and (w[8],A1,B1);
xnor (w[9],A0,B0);
and (w[10],w[8],w[9]);
and (w[11],w[1],w[2],B0,B1);
or (F,w[7],w[10],w[11]);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

===================================================

行為模式ver.1

module top;
wire A0,A1,B0,B1;
wire F;

system_clock #100 X1(B1);
system_clock #200 X1(B0);
system_clock #400 X1(A1);
system_clock #800 X1(A0);

testing1 Z1(F,A0,A1,B0,B1);
endmodule

module testing1(F,A0,A1,B0,B1);
input A0,A1,B0,B1;
output F;

assign F=A0&(~B0)&(~B1)A0&(~A1)&(~B0)(~A0)&A1&(~B0)&B1(~A0)&(~A1)&B0&B1A0&A1&B0&B1;

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

test_Nand_Latch_1 有tpd

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;

Nand_Latch_1 K1(q,qbar,preset,clear);

initial
begin
$monitor($time,"preset=%b clear==%b q=%b qbar=%b",preset,clear,q,qbar);
end

initial
begin
#10 preset=0;clear=1;
#10 preset=1; $stop;
#10 clear=0;
#10 clear=1;
#10 preset=0;
end

initial
#60 $finish;
endmodule



module Nand_Latch_1(q,qbar,preset,clear);
output q,qbar;
input preset,clear;

nand_a G1(q,preset,qbar),
G2(qbar,clear,q);
endmodule


module nand_a(C,A,B);
input A,B;
output C;

nand (C,A,B);

specify
specparam
Tpd_0_1=5:5:5,
Tpd_1_0=5:5:5;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

test_Nand_Latch_1

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;

Nand_Latch_1 K1(q,qbar,preset,clear);

initial
begin
$monitor($time,"preset=%b clear==%b q=%b qbar=%b",preset,clear,q,qbar);
end

initial
begin
#10 preset=0;clear=1;
#10 preset=1;$stop;
#10 clear=0;
#10 clear=1;
#10 preset=0;
end

initial
#60 $finish;
endmodule



module Nand_Latch_1(q,qbar,preset,clear);
output q,qbar;
input preset,clear;

nand G1(q,preset,qbar),
G2(qbar,clear,q);
endmodule

and-inverter test

module top;
wire A1,A2,B1,B2;
wire C1,C2,D1,D2;
system_clock #60 clock1(A1);
system_clock #40 clock1(A2);
system_clock #30 clock1(B1);
system_clock #20 clock1(B2);
and_a K1(C1,A1,B1);
and_a K2(C2,A2,B2);
inverter_a S1(D1,C1);
inverter_a S2(D2,C2);
endmodule

module and_a(C,A,B);
input A,B;
output C;

and (C,A,B);

specify
specparam
Tpd_0_1=3:3:3,
Tpd_1_0=3:3:3;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module inverter_a(D,C);
input C;
output D;

not (D,C);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(C=>D)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
endalways@(posedge clk)
if($time>1000)
#(PERIOD-1)
$stop;
endmodule

NAND-inverter TEST

module top;
wire A1,A2,B1,B2;
wire C1,C2,D1,D2;
system_clock #60 clock1(A1);
system_clock #40 clock1(A2);
system_clock #30 clock1(B1);
system_clock #20 clock1(B2);
nand_a K1(C1,A1,B1);
nand_a K2(C2,A2,B2);
inverter_a S1(D1,C1);
inverter_a S2(D2,C2);
endmodule

module nand_a(C,A,B);
input A,B;
output C;

nand (C,A,B);

specify
specparam
Tpd_0_1=3:3:3,
Tpd_1_0=3:3:3;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module inverter_a(D,C);
input C;
output D;

not (D,C);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(C=>D)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

inverter_simulation

module top;
wire X1,X2;
wire Y1,Y2;
system_clock #20 clock1(X1);
system_clock #15 clock1(X2);
inverter_a S1(Y1,X1);
inverter_a S2(Y2,X2);
endmodule

module inverter_a(Y,X);
input X;
output Y;

not (Y,X);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(X=>Y)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_algo

module top;
wire [1:0] A,B;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A[0]);
system_clock #100 clock1(A[1]);
system_clock #75 clock1(B[0]);
system_clock #150 clock1(B[1]);
compare_2_algo N1(A_lt_B,A_gt_B,A_eq_B,A,B);
endmodule

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output A_lt_B,A_gt_B,A_eq_B;
reg A_lt_B,A_gt_B,A_eq_B;

always@(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B) A_eq_B=1;
else if(A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_b

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_b X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_b(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B=({A1,A0}<{B1,B0});
assign A_gt_B=({A1,A0}>{B1,B0});
assign A_eq_B=({A1,A0}=={B1,B0});
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_str

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_str X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire [6:0]w;

not (w[0],A1);
not (w[1],A0);
and (w[2],w[0],B1);
and (w[3],w[0],w[1],B0);
and (w[4],w[1],B0,B1);
or (A_lt_B,w[2],w[3],w[4]);
xnor (w[5],A1,B1);
xnor (w[6],A0,B0);
and (A_eq_B,w[5],w[6]);
nor (A_gt_B,A_lt_B,A_eq_B);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_a

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_a X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_a(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B=(~A0)&B1(~A0)&(~A1)&B1(~A1)&B0&B1;
assign A_gt_B=A0&(~B0)A0&A1&(~B1)A1&(~B0)&(~B1);
assign A_eq_B=(~A0)&(~A1)&(~B0)&(~B1)(~A0)&A1&(~B0)&B1A0&A1&B0&B1A0&(~A1)&B0&(~B1);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

A_eg_B

A_eg_B=(~A0)(~A1)(~B0)(~B1)+(~A0)A1(~B0)B1+A0A1B0B1+A0
(~A1)B0(~B1)

=(~A1)(~B1){(~A0)(~B0)+A0B0}+A1B1{(~A0)(~B0)+A0B0}

={(~A0)(~B0)+A0B0}{(~A1)(~B1)+A1B1}

={A0 xnor B0} & {A1 xnor B1}

A_lt_B

00 01 11 10
00 1 1 1
01 1 1
11
10 1

(1)
A0 1
A1 0,1
B0 1
B1 0,1

=(~A0)B1

(2)
A0 0
A1 0
B0 0,1
B1 1

=(~A0)(~A1)B1

(3)
A0 0,1
A1 0
B0 1
B1 1

=(~A1)B0B1


A_lt_B=(~A0)B1 + (~A0)(~A1)B1 + (~A1)B0B1

16BIT全加器(ver0.3)

module top;
wire [15:0]a,b,sum;
wire c_out,c_in;
system_clock #1 clock1(a[0]);
system_clock #2 clock1(a[1]);
system_clock #4 clock1(a[2]);
system_clock #8 clock1(a[3]);
system_clock #16 clock1(a[4]);
system_clock #32 clock1(a[5]);
system_clock #64 clock1(a[6]);
system_clock #128 clock1(a[7]);
system_clock #256 clock1(a[8]);
system_clock #512 clock1(a[9]);
system_clock #1024 clock1(a[10]);
system_clock #2048 clock1(a[11]);
system_clock #4096 clock1(a[12]);
system_clock #8192 clock1(a[13]);
system_clock #16384 clock1(a[14]);
system_clock #32768 clock1(a[15]);

system_clock #98304 clock1(b[15]);
system_clock #49152 clock1(b[14]);
system_clock #24576 clock1(b[13]);
system_clock #12288 clock1(b[12]);
system_clock #6144 clock1(b[11]);
system_clock #3072 clock1(b[10]);
system_clock #1536 clock1(b[9]);
system_clock #768 clock1(b[8]);
system_clock #384 clock1(b[7]);
system_clock #192 clock1(b[6]);
system_clock #96 clock1(b[5]);
system_clock #48 clock1(b[4]);
system_clock #24 clock1(b[3]);
system_clock #12 clock1(b[2]);
system_clock #6 clock1(b[1]);
system_clock #3 clock1(b[0]);

system_clock #5000 clock1(c_in);

Add_16bit D1(sum,c_out,a,b,c_in);
endmodule


module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule


module Add_Full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule


module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire r1,r2,r3;
Add_Full M1(sum[0],r1,a[0],b[0],c_in);
Add_Full M2(sum[1],r2,a[1],b[1],r1);
Add_Full M3(sum[2],r3,a[2],b[2],r2);
Add_Full M4(sum[3],c_out,a[3],b[3],r3);
endmodule


module Add_16bit(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire s1,s2,s3;
Add_4bit Z1(sum[3:0],s1,a[3:0],b[3:0],c_in);
Add_4bit Z2(sum[7:4],s2,a[7:4],b[7:4],s1);
Add_4bit Z3(sum[11:8],s3,a[11:8],b[11:8],s2);
Add_4bit Z4(sum[15:12],c_out,a[15:12],b[15:12],s3);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>100000)#(PERIOD-1)$stop;
endmodule

4BIT全加器(行為模式)

module top;
wire [3:0]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[0]);
system_clock #200 clock1(a[1]);
system_clock #100 clock1(a[2]);
system_clock #50 clock1(a[3]);
system_clock #600 clock1(b[0]);
system_clock #300 clock1(b[1]);
system_clock #150 clock1(b[2]);
system_clock #75 clock1(b[3]);
system_clock #5000 clock1(c_in);
Add_4bit D1(sum,c_out,a,b,c_in);
endmodule

module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b,c_in;
output [3:0]sum;
output c_out;
assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

4-bit 全加器

module top;
wire [3:0]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[0]);
system_clock #200 clock1(a[1]);
system_clock #100 clock1(a[2]);
system_clock #50 clock1(a[3]);
system_clock #600 clock1(b[0]);
system_clock #300 clock1(b[1]);
system_clock #150 clock1(b[2]);
system_clock #75 clock1(b[3]);
system_clock #5000 clock1(c_in);
Add_4bit D1(sum,c_out,a,b,c_in);
endmodule

module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
Add_Full M1(sum[0],w1,a[0],b[0],c_in);
Add_Full M2(sum[1],w2,a[1],b[1],w1);
Add_Full M3(sum[2],w3,a[2],b[2],w2);
Add_Full M4(sum[3],c_out,a[3],b[3],w3);
endmodule

module Add_Full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule

module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

全加器(行為模式)

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);system_clock #50 clock1(b);
system_clock #200 clock1(c_in);
Add_Full M1(sum,c,a,b,c_in);
endmodule

module Add_Full(Sum,C_out,a,b,c_in);
input a,b,c_in;
output Sum,C_out;
wire w1,w2,w3;
assign {C_out,Sum} = a + b + c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

全加器

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);system_clock #200 clock1(c_in);
Add_Full M1(sum,c,a,b,c_in);
endmodule

module Add_Full(Sum,C_out,a,b,c_in);
input a,b,c_in;
output Sum,C_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(Sum,w3,w1,c_in);
or (C_out,w2,w3);
endmodule

module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加法器

module top;
wire a,b;
wire sum,c; system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half M1(sum,c,a,b);
endmodule

module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule