inverter_simulation

module top;
wire X1,X2;
wire Y1,Y2;
system_clock #20 clock1(X1);
system_clock #15 clock1(X2);
inverter_a S1(Y1,X1);
inverter_a S2(Y2,X2);
endmodule

module inverter_a(Y,X);
input X;
output Y;

not (Y,X);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(X=>Y)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule