and-inverter test

module top;
wire A1,A2,B1,B2;
wire C1,C2,D1,D2;
system_clock #60 clock1(A1);
system_clock #40 clock1(A2);
system_clock #30 clock1(B1);
system_clock #20 clock1(B2);
and_a K1(C1,A1,B1);
and_a K2(C2,A2,B2);
inverter_a S1(D1,C1);
inverter_a S2(D2,C2);
endmodule

module and_a(C,A,B);
input A,B;
output C;

and (C,A,B);

specify
specparam
Tpd_0_1=3:3:3,
Tpd_1_0=3:3:3;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module inverter_a(D,C);
input C;
output D;

not (D,C);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(C=>D)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
endalways@(posedge clk)
if($time>1000)
#(PERIOD-1)
$stop;
endmodule