compare_2_algo

module top;
wire [1:0] A,B;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A[0]);
system_clock #100 clock1(A[1]);
system_clock #75 clock1(B[0]);
system_clock #150 clock1(B[1]);
compare_2_algo N1(A_lt_B,A_gt_B,A_eq_B,A,B);
endmodule

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output A_lt_B,A_gt_B,A_eq_B;
reg A_lt_B,A_gt_B,A_eq_B;

always@(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B) A_eq_B=1;
else if(A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule