期中考

A0 A1 B0 B1 F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

F={A0(~B0)(~B1)}+{A0(~A1)(~B0)}+{(~A0)A1(~B0)B1}+{(~A0)(~A1)B0B1}+{A0A1B0B1}

={A0(~B0)[(~A1)+(~B1)]} + {A1B1[(~A0)(~B0)+A0B0]} + {(~A0)(~A1)B0B1}

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module top;
wire A0,A1,B0,B1;
wire F;

system_clock #100 X1(B1);
system_clock #200 X1(B0);
system_clock #400 X1(A1);
system_clock #800 X1(A0);

testing1 Z1(F,A0,A1,B0,B1);
endmodule

module testing1(F,A0,A1,B0,B1);
input A0,A1,B0,B1;
output F;
wire [11:1] w;

not (w[1],A0);
not (w[2],A1);
not (w[3],B0);
not (w[4],B1);
and (w[5],A0,w[3]);
or (w[6],w[2],w[4]);
and (w[7],w[5],w[6]);
and (w[8],A1,B1);
xnor (w[9],A0,B0);
and (w[10],w[8],w[9]);
and (w[11],w[1],w[2],B0,B1);
or (F,w[7],w[10],w[11]);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

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行為模式ver.1

module top;
wire A0,A1,B0,B1;
wire F;

system_clock #100 X1(B1);
system_clock #200 X1(B0);
system_clock #400 X1(A1);
system_clock #800 X1(A0);

testing1 Z1(F,A0,A1,B0,B1);
endmodule

module testing1(F,A0,A1,B0,B1);
input A0,A1,B0,B1;
output F;

assign F=A0&(~B0)&(~B1)A0&(~A1)&(~B0)(~A0)&A1&(~B0)&B1(~A0)&(~A1)&B0&B1A0&A1&B0&B1;

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule