4BIT全加器(行為模式)

module top;
wire [3:0]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[0]);
system_clock #200 clock1(a[1]);
system_clock #100 clock1(a[2]);
system_clock #50 clock1(a[3]);
system_clock #600 clock1(b[0]);
system_clock #300 clock1(b[1]);
system_clock #150 clock1(b[2]);
system_clock #75 clock1(b[3]);
system_clock #5000 clock1(c_in);
Add_4bit D1(sum,c_out,a,b,c_in);
endmodule

module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b,c_in;
output [3:0]sum;
output c_out;
assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule