compare_2_a

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_a X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_a(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B=(~A0)&B1(~A0)&(~A1)&B1(~A1)&B0&B1;
assign A_gt_B=A0&(~B0)A0&A1&(~B1)A1&(~B0)&(~B1);
assign A_eq_B=(~A0)&(~A1)&(~B0)&(~B1)(~A0)&A1&(~B0)&B1A0&A1&B0&B1A0&(~A1)&B0&(~B1);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule