compare_2_str

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_str X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire [6:0]w;

not (w[0],A1);
not (w[1],A0);
and (w[2],w[0],B1);
and (w[3],w[0],w[1],B0);
and (w[4],w[1],B0,B1);
or (A_lt_B,w[2],w[3],w[4]);
xnor (w[5],A1,B1);
xnor (w[6],A0,B0);
and (A_eq_B,w[5],w[6]);
nor (A_gt_B,A_lt_B,A_eq_B);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule