4-bit 全加器

module top;
wire [3:0]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[0]);
system_clock #200 clock1(a[1]);
system_clock #100 clock1(a[2]);
system_clock #50 clock1(a[3]);
system_clock #600 clock1(b[0]);
system_clock #300 clock1(b[1]);
system_clock #150 clock1(b[2]);
system_clock #75 clock1(b[3]);
system_clock #5000 clock1(c_in);
Add_4bit D1(sum,c_out,a,b,c_in);
endmodule

module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
Add_Full M1(sum[0],w1,a[0],b[0],c_in);
Add_Full M2(sum[1],w2,a[1],b[1],w1);
Add_Full M3(sum[2],w3,a[2],b[2],w2);
Add_Full M4(sum[3],c_out,a[3],b[3],w3);
endmodule

module Add_Full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule

module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule