全加器

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);system_clock #200 clock1(c_in);
Add_Full M1(sum,c,a,b,c_in);
endmodule

module Add_Full(Sum,C_out,a,b,c_in);
input a,b,c_in;
output Sum,C_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(Sum,w3,w1,c_in);
or (C_out,w2,w3);
endmodule

module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule