16BIT全加器(ver0.3)

module top;
wire [15:0]a,b,sum;
wire c_out,c_in;
system_clock #1 clock1(a[0]);
system_clock #2 clock1(a[1]);
system_clock #4 clock1(a[2]);
system_clock #8 clock1(a[3]);
system_clock #16 clock1(a[4]);
system_clock #32 clock1(a[5]);
system_clock #64 clock1(a[6]);
system_clock #128 clock1(a[7]);
system_clock #256 clock1(a[8]);
system_clock #512 clock1(a[9]);
system_clock #1024 clock1(a[10]);
system_clock #2048 clock1(a[11]);
system_clock #4096 clock1(a[12]);
system_clock #8192 clock1(a[13]);
system_clock #16384 clock1(a[14]);
system_clock #32768 clock1(a[15]);

system_clock #98304 clock1(b[15]);
system_clock #49152 clock1(b[14]);
system_clock #24576 clock1(b[13]);
system_clock #12288 clock1(b[12]);
system_clock #6144 clock1(b[11]);
system_clock #3072 clock1(b[10]);
system_clock #1536 clock1(b[9]);
system_clock #768 clock1(b[8]);
system_clock #384 clock1(b[7]);
system_clock #192 clock1(b[6]);
system_clock #96 clock1(b[5]);
system_clock #48 clock1(b[4]);
system_clock #24 clock1(b[3]);
system_clock #12 clock1(b[2]);
system_clock #6 clock1(b[1]);
system_clock #3 clock1(b[0]);

system_clock #5000 clock1(c_in);

Add_16bit D1(sum,c_out,a,b,c_in);
endmodule


module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule


module Add_Full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule


module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire r1,r2,r3;
Add_Full M1(sum[0],r1,a[0],b[0],c_in);
Add_Full M2(sum[1],r2,a[1],b[1],r1);
Add_Full M3(sum[2],r3,a[2],b[2],r2);
Add_Full M4(sum[3],c_out,a[3],b[3],r3);
endmodule


module Add_16bit(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire s1,s2,s3;
Add_4bit Z1(sum[3:0],s1,a[3:0],b[3:0],c_in);
Add_4bit Z2(sum[7:4],s2,a[7:4],b[7:4],s1);
Add_4bit Z3(sum[11:8],s3,a[11:8],b[11:8],s2);
Add_4bit Z4(sum[15:12],c_out,a[15:12],b[15:12],s3);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>100000)#(PERIOD-1)$stop;
endmodule