1位元全加法器(with UDP)

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
system_clock #200 clock1(c_in);

Adder_Sum D1(sum,a,b,c_in);
Adder_C D2(c,a,b,c_in);
endmodule

primitive Adder_Sum(Sum,A,B,C_in);
output Sum;
input C_in,A,B;

table
// C_in A B : Sum
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 0;
1 1 1 : 1;
endtable
endprimitive

primitive Adder_C(C,A,B,C_in);
output C;
input C_in,A,B;
table
// C_in A B : C
0 0 0 : 0;
0 0 1 : 0;
0 1 0 : 0;
0 1 1 : 1;
1 0 0 : 0;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;

endtable
endprimitive

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule