compare_2_b

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_b X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_b(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B=({A1,A0}<{B1,B0});
assign A_gt_B=({A1,A0}>{B1,B0});
assign A_eq_B=({A1,A0}=={B1,B0});
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_str

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_str X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire [6:0]w;

not (w[0],A1);
not (w[1],A0);
and (w[2],w[0],B1);
and (w[3],w[0],w[1],B0);
and (w[4],w[1],B0,B1);
or (A_lt_B,w[2],w[3],w[4]);
xnor (w[5],A1,B1);
xnor (w[6],A0,B0);
and (A_eq_B,w[5],w[6]);
nor (A_gt_B,A_lt_B,A_eq_B);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_a

module top;
wire A0,A1,B0,B1;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A0);
system_clock #100 clock1(A1);
system_clock #75 clock1(B0);
system_clock #150 clock1(B1);
compare_2_a X1(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
endmodule

module compare_2_a(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B=(~A0)&B1(~A0)&(~A1)&B1(~A1)&B0&B1;
assign A_gt_B=A0&(~B0)A0&A1&(~B1)A1&(~B0)&(~B1);
assign A_eq_B=(~A0)&(~A1)&(~B0)&(~B1)(~A0)&A1&(~B0)&B1A0&A1&B0&B1A0&(~A1)&B0&(~B1);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

A_eg_B

A_eg_B=(~A0)(~A1)(~B0)(~B1)+(~A0)A1(~B0)B1+A0A1B0B1+A0
(~A1)B0(~B1)

=(~A1)(~B1){(~A0)(~B0)+A0B0}+A1B1{(~A0)(~B0)+A0B0}

={(~A0)(~B0)+A0B0}{(~A1)(~B1)+A1B1}

={A0 xnor B0} & {A1 xnor B1}

A_lt_B

00 01 11 10
00 1 1 1
01 1 1
11
10 1

(1)
A0 1
A1 0,1
B0 1
B1 0,1

=(~A0)B1

(2)
A0 0
A1 0
B0 0,1
B1 1

=(~A0)(~A1)B1

(3)
A0 0,1
A1 0
B0 1
B1 1

=(~A1)B0B1


A_lt_B=(~A0)B1 + (~A0)(~A1)B1 + (~A1)B0B1

16BIT全加器(ver0.3)

module top;
wire [15:0]a,b,sum;
wire c_out,c_in;
system_clock #1 clock1(a[0]);
system_clock #2 clock1(a[1]);
system_clock #4 clock1(a[2]);
system_clock #8 clock1(a[3]);
system_clock #16 clock1(a[4]);
system_clock #32 clock1(a[5]);
system_clock #64 clock1(a[6]);
system_clock #128 clock1(a[7]);
system_clock #256 clock1(a[8]);
system_clock #512 clock1(a[9]);
system_clock #1024 clock1(a[10]);
system_clock #2048 clock1(a[11]);
system_clock #4096 clock1(a[12]);
system_clock #8192 clock1(a[13]);
system_clock #16384 clock1(a[14]);
system_clock #32768 clock1(a[15]);

system_clock #98304 clock1(b[15]);
system_clock #49152 clock1(b[14]);
system_clock #24576 clock1(b[13]);
system_clock #12288 clock1(b[12]);
system_clock #6144 clock1(b[11]);
system_clock #3072 clock1(b[10]);
system_clock #1536 clock1(b[9]);
system_clock #768 clock1(b[8]);
system_clock #384 clock1(b[7]);
system_clock #192 clock1(b[6]);
system_clock #96 clock1(b[5]);
system_clock #48 clock1(b[4]);
system_clock #24 clock1(b[3]);
system_clock #12 clock1(b[2]);
system_clock #6 clock1(b[1]);
system_clock #3 clock1(b[0]);

system_clock #5000 clock1(c_in);

Add_16bit D1(sum,c_out,a,b,c_in);
endmodule


module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule


module Add_Full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule


module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire r1,r2,r3;
Add_Full M1(sum[0],r1,a[0],b[0],c_in);
Add_Full M2(sum[1],r2,a[1],b[1],r1);
Add_Full M3(sum[2],r3,a[2],b[2],r2);
Add_Full M4(sum[3],c_out,a[3],b[3],r3);
endmodule


module Add_16bit(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire s1,s2,s3;
Add_4bit Z1(sum[3:0],s1,a[3:0],b[3:0],c_in);
Add_4bit Z2(sum[7:4],s2,a[7:4],b[7:4],s1);
Add_4bit Z3(sum[11:8],s3,a[11:8],b[11:8],s2);
Add_4bit Z4(sum[15:12],c_out,a[15:12],b[15:12],s3);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>100000)#(PERIOD-1)$stop;
endmodule

4BIT全加器(行為模式)

module top;
wire [3:0]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[0]);
system_clock #200 clock1(a[1]);
system_clock #100 clock1(a[2]);
system_clock #50 clock1(a[3]);
system_clock #600 clock1(b[0]);
system_clock #300 clock1(b[1]);
system_clock #150 clock1(b[2]);
system_clock #75 clock1(b[3]);
system_clock #5000 clock1(c_in);
Add_4bit D1(sum,c_out,a,b,c_in);
endmodule

module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b,c_in;
output [3:0]sum;
output c_out;
assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

4-bit 全加器

module top;
wire [3:0]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[0]);
system_clock #200 clock1(a[1]);
system_clock #100 clock1(a[2]);
system_clock #50 clock1(a[3]);
system_clock #600 clock1(b[0]);
system_clock #300 clock1(b[1]);
system_clock #150 clock1(b[2]);
system_clock #75 clock1(b[3]);
system_clock #5000 clock1(c_in);
Add_4bit D1(sum,c_out,a,b,c_in);
endmodule

module Add_4bit(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
Add_Full M1(sum[0],w1,a[0],b[0],c_in);
Add_Full M2(sum[1],w2,a[1],b[1],w1);
Add_Full M3(sum[2],w3,a[2],b[2],w2);
Add_Full M4(sum[3],c_out,a[3],b[3],w3);
endmodule

module Add_Full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule

module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

全加器(行為模式)

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);system_clock #50 clock1(b);
system_clock #200 clock1(c_in);
Add_Full M1(sum,c,a,b,c_in);
endmodule

module Add_Full(Sum,C_out,a,b,c_in);
input a,b,c_in;
output Sum,C_out;
wire w1,w2,w3;
assign {C_out,Sum} = a + b + c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

全加器

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);system_clock #200 clock1(c_in);
Add_Full M1(sum,c,a,b,c_in);
endmodule

module Add_Full(Sum,C_out,a,b,c_in);
input a,b,c_in;
output Sum,C_out;
wire w1,w2,w3;
Add_half X1(w1,w2,a,b);
Add_half X2(Sum,w3,w1,c_in);
or (C_out,w2,w3);
endmodule

module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加法器

module top;
wire a,b;
wire sum,c; system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half M1(sum,c,a,b);
endmodule

module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule