32位元加法 Ver.未測試1

module top;
wire c_out,c_in,c_out2;
reg [31:0]a,b,a2,b2;
wire [31:0]sum,sum2;
integer a1,b1,a11,b11;

system_clock #200 clock9(c_in);

initial
begin
for(a1=0;a1<65536;a1=a1+1)
begin
for(a11=0;a11<65536;a11=a11+1)
begin
for (b1=0;b1<65536;b1=b1+1)
begin
for (b11=0;b11<65536;b11=b11+1)
begin
{b}=b11;
{a}=a11;
{b2}=b11;
{a2}=a11;
#1;
end
end
end
end
$finish;
end
Adder_x #32 K1(sum,c_out,a,b,c_in);
assign {c_out2,sum2}=a2+b2+c_in;
always@(a2 or b2 or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o,a2=%o,a1=%o,b2=%o,b1=%o",sum,sum2,a2,a,b2,b);
else
$display ("c_out=%b,c_out2=%b,a2=%o,a1=%o,b2=%o,b1=%o",c_out,c_out2,a2,a,b2,b);
end
endmodule



module Adder_x(sum,c_out,a,b,c_in);
parameter size=4;
input [size-1:0]a,b,c_in;
output [size-1:0]sum;
output c_out;

assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

期中考

A0 A1 B0 B1 F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

F={A0(~B0)(~B1)}+{A0(~A1)(~B0)}+{(~A0)A1(~B0)B1}+{(~A0)(~A1)B0B1}+{A0A1B0B1}

={A0(~B0)[(~A1)+(~B1)]} + {A1B1[(~A0)(~B0)+A0B0]} + {(~A0)(~A1)B0B1}

====================================================

module top;
wire A0,A1,B0,B1;
wire F;

system_clock #100 X1(B1);
system_clock #200 X1(B0);
system_clock #400 X1(A1);
system_clock #800 X1(A0);

testing1 Z1(F,A0,A1,B0,B1);
endmodule

module testing1(F,A0,A1,B0,B1);
input A0,A1,B0,B1;
output F;
wire [11:1] w;

not (w[1],A0);
not (w[2],A1);
not (w[3],B0);
not (w[4],B1);
and (w[5],A0,w[3]);
or (w[6],w[2],w[4]);
and (w[7],w[5],w[6]);
and (w[8],A1,B1);
xnor (w[9],A0,B0);
and (w[10],w[8],w[9]);
and (w[11],w[1],w[2],B0,B1);
or (F,w[7],w[10],w[11]);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

===================================================

行為模式ver.1

module top;
wire A0,A1,B0,B1;
wire F;

system_clock #100 X1(B1);
system_clock #200 X1(B0);
system_clock #400 X1(A1);
system_clock #800 X1(A0);

testing1 Z1(F,A0,A1,B0,B1);
endmodule

module testing1(F,A0,A1,B0,B1);
input A0,A1,B0,B1;
output F;

assign F=A0&(~B0)&(~B1)A0&(~A1)&(~B0)(~A0)&A1&(~B0)&B1(~A0)&(~A1)&B0&B1A0&A1&B0&B1;

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

test_Nand_Latch_1 有tpd

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;

Nand_Latch_1 K1(q,qbar,preset,clear);

initial
begin
$monitor($time,"preset=%b clear==%b q=%b qbar=%b",preset,clear,q,qbar);
end

initial
begin
#10 preset=0;clear=1;
#10 preset=1; $stop;
#10 clear=0;
#10 clear=1;
#10 preset=0;
end

initial
#60 $finish;
endmodule



module Nand_Latch_1(q,qbar,preset,clear);
output q,qbar;
input preset,clear;

nand_a G1(q,preset,qbar),
G2(qbar,clear,q);
endmodule


module nand_a(C,A,B);
input A,B;
output C;

nand (C,A,B);

specify
specparam
Tpd_0_1=5:5:5,
Tpd_1_0=5:5:5;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

test_Nand_Latch_1

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;

Nand_Latch_1 K1(q,qbar,preset,clear);

initial
begin
$monitor($time,"preset=%b clear==%b q=%b qbar=%b",preset,clear,q,qbar);
end

initial
begin
#10 preset=0;clear=1;
#10 preset=1;$stop;
#10 clear=0;
#10 clear=1;
#10 preset=0;
end

initial
#60 $finish;
endmodule



module Nand_Latch_1(q,qbar,preset,clear);
output q,qbar;
input preset,clear;

nand G1(q,preset,qbar),
G2(qbar,clear,q);
endmodule

and-inverter test

module top;
wire A1,A2,B1,B2;
wire C1,C2,D1,D2;
system_clock #60 clock1(A1);
system_clock #40 clock1(A2);
system_clock #30 clock1(B1);
system_clock #20 clock1(B2);
and_a K1(C1,A1,B1);
and_a K2(C2,A2,B2);
inverter_a S1(D1,C1);
inverter_a S2(D2,C2);
endmodule

module and_a(C,A,B);
input A,B;
output C;

and (C,A,B);

specify
specparam
Tpd_0_1=3:3:3,
Tpd_1_0=3:3:3;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module inverter_a(D,C);
input C;
output D;

not (D,C);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(C=>D)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
endalways@(posedge clk)
if($time>1000)
#(PERIOD-1)
$stop;
endmodule

NAND-inverter TEST

module top;
wire A1,A2,B1,B2;
wire C1,C2,D1,D2;
system_clock #60 clock1(A1);
system_clock #40 clock1(A2);
system_clock #30 clock1(B1);
system_clock #20 clock1(B2);
nand_a K1(C1,A1,B1);
nand_a K2(C2,A2,B2);
inverter_a S1(D1,C1);
inverter_a S2(D2,C2);
endmodule

module nand_a(C,A,B);
input A,B;
output C;

nand (C,A,B);

specify
specparam
Tpd_0_1=3:3:3,
Tpd_1_0=3:3:3;

(A=>C)=(Tpd_0_1,Tpd_1_0);
(B=>C)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module inverter_a(D,C);
input C;
output D;

not (D,C);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(C=>D)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

inverter_simulation

module top;
wire X1,X2;
wire Y1,Y2;
system_clock #20 clock1(X1);
system_clock #15 clock1(X2);
inverter_a S1(Y1,X1);
inverter_a S2(Y2,X2);
endmodule

module inverter_a(Y,X);
input X;
output Y;

not (Y,X);

specify
specparam
Tpd_0_1=2:2:2,
Tpd_1_0=2:2:2;

(X=>Y)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

compare_2_algo

module top;
wire [1:0] A,B;
wire A_lt_B,A_gt_B,A_eq_B;
system_clock #50 clock1(A[0]);
system_clock #100 clock1(A[1]);
system_clock #75 clock1(B[0]);
system_clock #150 clock1(B[1]);
compare_2_algo N1(A_lt_B,A_gt_B,A_eq_B,A,B);
endmodule

module compare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output A_lt_B,A_gt_B,A_eq_B;
reg A_lt_B,A_gt_B,A_eq_B;

always@(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B) A_eq_B=1;
else if(A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule