Non-blocking assignment

module top();
reg A1,A2,B1,B2;

initial begin //Non-blocking assignment
A1=1;
B1=0;
A1<=B1;
B1<=A1;
end

initial begin //Blocking assignment
A2=1;
B2=0;
A2=B2;
B2=A2;
end

initial begin
$monitor("A1=%b B1=%b A2=%b B2=%b",A1,B1,A2,B2);
end

endmodule

Time scales Ex.3

`timescale 1ns/1ps
module The_first_module(y,x1,x2);
input x1,x2;
output y;

nand #(3.213:3.225:3.643,4.112:4.237:4.413) (y,x1,x2);
endmodule


`timescale 10ns/10ns
module The_second_module();
reg x1,x2;
wire y;

The_first_module K1(y,x1,x2);

initial begin
$timeformat(-12,1," ps",10);
$monitor($time,,"%f x1=%b x2=%b y=%b",$realtime,x1,x2,y);
end

initial #30 $finish;

initial begin
#5 x1=0;x2=0;
#5 x2=1;
#5 x1=1;
#5 x2=0;
#5 $stop;
end
endmodule

Time scales Ex.2

`timescale 1ns/1ps
module The_first_module(y,x1,x2);
input x1,x2;
output y;

nand #(3.213:3.225:3.643,4.112:4.237:4.413) (y,x1,x2);
endmodule


`timescale 10ns/10ns
module The_second_module();
reg x1,x2;
wire y;

The_first_module K1(y,x1,x2);

initial begin
$timeformat(-10,1,"x100ps",10);
$monitor($time,,"%f x1=%b x2=%b y=%b",$realtime,x1,x2,y);
end

initial #30 $finish;

initial begin
#5 x1=0;x2=0;
#5 x2=1;
#5 x1=1;
#5 x2=0;
#5 $stop;
end
endmodule

Time Scales Ex.1

`timescale 1ns/10ps
module The_first_module(y,x1,x2);
input x1,x2;
output y;

nand #(3.213:3.225:3.643,4.112:4.237:4.413) (y,x1,x2);
endmodule


`timescale 10ns/10ns
module The_second_module();
reg x1,x2;
wire y;

The_first_module K1(y,x1,x2);

initial begin
$timeformat(-10,1," x100ps",10);
$monitor($time,,"%f x1=%b x2=%b y=%b",$realtime,x1,x2,y);
end

initial #30 $finish;

initial begin
#5 x1=0;x2=0;
#5 x2=1;
#5 x1=1;
#5 x2=0;
#5 $stop;
end
endmodule

1位元全加法器(with UDP)

module top;
wire a,b,c_in;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
system_clock #200 clock1(c_in);

Adder_Sum D1(sum,a,b,c_in);
Adder_C D2(c,a,b,c_in);
endmodule

primitive Adder_Sum(Sum,A,B,C_in);
output Sum;
input C_in,A,B;

table
// C_in A B : Sum
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 0;
1 1 1 : 1;
endtable
endprimitive

primitive Adder_C(C,A,B,C_in);
output C;
input C_in,A,B;
table
// C_in A B : C
0 0 0 : 0;
0 0 1 : 0;
0 1 0 : 0;
0 1 1 : 1;
1 0 0 : 0;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;

endtable
endprimitive

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

危障

module top;
wire f,c_bar,d,e,f0,f1;
reg a,b,c;
initial
begin
#10 a=1; b=1;
#10 c=1;
#10 c=0;
end
initial
#100 $finish;


AND_gate xxx(f0,a,c);
NOT xxx1(c_bar,c);
AND_gate xxx2(f1,b,c_bar);
or_data xx(f,f0,f1);

AND_gate xxx3(f3,a,b);
AND_gate xxx(f4,a,c);
AND_gate xxx2(f5,b,c_bar);
or_data2 xx1(f2,f3,f4,f5);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module NOT(c_bar,c);
input c;
output c_bar;
wire c;
not(c_bar,c);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(c=>c_bar)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data(f,f0,f1);
input f0,f1;
output f;
wire f;
or(f,f0,f1);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f0=>f)=(Tpd_0_1,Tpd_1_0);
(f1=>f)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data2(f2,f3,f4,f5);
input f3,f4,f5;
output f2;
wire f2;

or(f2,f3,f4,f5);

specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f3=>f2)=(Tpd_0_1,Tpd_1_0);
(f4=>f2)=(Tpd_0_1,Tpd_1_0);
(f5=>f2)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule